Senior FPGA Designer
Working in a development team, the successful candidate will get the opportunity to help shape the future of the video broadcast industry.
Duties and Responsibilities:
- Work with the team (Manager, HW & SW) to develop high-level design requirement, device selection and project schedules.
- Design, develop, simulate and test FPGA designs as per product specifications or product line guidelines.
- Work with other members of the team to verify the functionality of the FPGA.
- Generate interface documentation to other hardware and software team members.
- Review schematics and design documents as required, pertaining to the FPGA interface and functionality, and peer review the work of colleagues.
- Troubleshoot, debug and fix FPGA issues and related problems as required.
- Assist in training other staff members; mentor more junior staff.
- Report project and task status as required.
- Perform other related duties as required.
- You are an expert in RTL design for complex IP targeting large Xilinx and Altera FPGA SOC.
- Recent experience with Altera and Xilinx design software including synthesis, SOC design tools and timing closure.
- Verilog/System Verilog RTL experience.
- Experience working with scripted tool flow (tcl, perl, sh), source control.
- Experience working with lab equipment to debug complex designs that could involve multiple people.
- Familiar with video broadcast standards such as SDI, AES, Timecode, Madi, Tri-level syncs.
- Familiar with high speed serial interfaces such as SDI, 10 GigE, Ethernet, PCle.
- Experience designing video processing algorithms such as filters or video codecs (H264, H265, MPEG2).
- Work experience with constrained random verification methodology such as VMM or UVM.
- Experience working with high speed memory interface such as DDR3/4.
- Experience designing software model in C/C++ to perform algorithm exploration at a high level.
- Experience with the creation of code generation tool and workflow automation.
- Experience with higher level synthesis flow using C or OpenCL.
- Office, Moderate Noise.